This invention relates to the manufacture of semiconductor circuit devices. More specifically the invention relates to manufacture of multilayer semiconductor circuit devices in which photomasking steps are used in the manufacture.
The invention uses various materials which are electrically either conductive, insulative or semiconductive, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is polysilicon material, referred to as "poly" throughout this disclosure.
The invention is used in a complete fabrication process for a cost-effective manufacturable means of high volume production of NMOS high density dynamic random access memories (DRAMs). It is called the reverse poly DRAM process. It requires only 7 photomasking steps total (including bond pad level) to produce high quality, high density NMOS DRAMs. This process is applicable to latest generation DRAM memory devices from 64 Kbit up through 1 Megbit density generations and beyond.
While the invention is described in terms of DRAMs, this is merely the preferred embodiment for which the inventive techniques were developed. The reverse poly DRAM process techniques are also applicable to related semiconductor circuit devices, including video random access memories (VRAMs) and other multiport RAMS, and other devices which use DRAM design techniques, such as optical sensing arrays. The reverse poly DRAM process techniques may be applicable to other types of semiconductor devices as well.
Producing DRAM IC memory circuits is a high volume business, in which process efficiency and manufacturability as well as product quality, reliability, and performance are essential key factors. This invention dramatically advances the "state of the art" in a number of ways in these areas.
The reverse poly DRAM process dramatically reduces the number of process steps, including masking steps, which has a direct impact on the cost, reliability, and manufacturability of the product. Latest generation DRAM products require scaling down to finer and finer geometries. This has a big impact on the cost of doing a photolithographic step. The source of this added cost comes from many sources. There are high capital costs associated with "state of the art" photolithographic equipment. Finer geometries require more complex photo processing in terms of more photo process steps per level and more equipment required, adding cost and using expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises line yield, probe yield, and reliability. All photo layers require a subsequent step, either implant or etch. These are added steps adding to cost.
For the reverse poly DRAM process, no extra mask steps for Vt adjust is required. In DRAM applications the threshold voltage of the array access transistors have seperate requirements from the peripheral transistors.
The access devices generally need a higher threshold than the periphery to optimize dynamic refresh characteritics. Peripheral transistors are optimized at reduced threshold values for maximum high speed performance.
The conventional solution to this is to seperately adjust the threshold of these two groups of transistors using a photomasking level. The reverse poly DRAM process has been designed in terms of thermal cycles (Dt) and layout such that these two criteria are simultaneously met without a seperate tayloring threshold adjust implant masking step required.
It is desired to improve yield and reliability and reduce manufacturing costs. This can be accomplished by reduced cycle times through fabrication, reduced total process inventory needed for a given run rate, more rapid response to process changes in volume quantities, more repeatable performance, and less number of steps to introduce variation. The process is shrinkable for subsequent generation products and the process flow fits in well with subsequent CMOS high density DRAM processes. The transistor structure is fully shrinkable while maintaining strong "long channel" characteristics, high performance, and minimal degradation with time (high reliability).
The process is compatible with today's IC fabrication equipment, not requiring exotic new equipment. It avoids problems with poly "stringers" or "sticks", a common problem with conventional DRAM process technology. The process reduces the number of high current implants from a conventional 2 to only 1 implant. This is a costly step in terms of both throughput and machine cost and is greatly advantageous to minimize. Self alignment of the cell capacitor dielectric region makes possible the use of a cell capacitor dielectric with reduced oxide thickness from the transistor gate oxide without having to define this with another masking level.
This same concept also makes it possible to use an alternative cell capacitor dielectric material with higher dielectric permittivity than conventional silicon dioxide. A higher permittivity dielectric results in increased cell capacitance per unit area. Higher cell capacitance improves immunity to single event upsets due to alpha particles or cosmic radiation. This results in higher operational reliability. It also reduces the amount of surface area needed for the cell capacitor, thus allowing for greater shrink and smaller die size. No extra photomasking step is required for this feature.
Poly 1 is used for the transistor poly and Poly 2 is used for the cell field plate poly. This is opposite of most other DRAM processes. As mentioned above, this approach offers advantages. The transistor poly photo patterning and etch critical dimension control is improved due to lack of concern for "Stringers" and extra topography.
"Stringer" problems are minimized since they are a factor only during Poly 2 etch.
Poly 2 etch for the reverse poly DRAM process is for patterning of the cell field plate which is a non-critical etch and can be done by a number of isotropic means. This insures complete etch removal of "Stringers". The extra topography seen at Poly 2 etch is less a factor due to the less stringent Cell plate poly etch tolerances required. Self-alignment is possible between the cell capacitor region and the access gate active channel region. There is less susceptability to field oxide thinning between Poly 1 and Poly 2. The high current/high dose arsenic S/D implant is done prior to cell capacitor formation. This spares the cell cap of having to withstand the electric field stress present due to charging effects associated with the S/D implant. This is a major factor as cell dielectrics continue to thin and become more and more sensitive to E-fields present during processing. The reverse poly DRAM process also offers the following product performance advantages. The invention makes possible use of advanced transistor structures using LDD with flexibility for re-optimization when shrinking in the future. The transistor structure also minimizes high drain electric fields thus helping preserve device stability and long term reliability. The reverse poly DRAM process is highly compatible with subsequent generation (multi-megabit) CMOS DRAMs allowing multi-generation parts to run in the same Fabrication area. Flexibility in cell capacitor dielectric is made possible by having the option of independently varying the transistor gate oxide independent of the cell capacitor dielectric. This flexibility is made possible without adding a photomasking step.